Traditional ASIC and IP verification methods cannot adequately exercise the hardware and software components of today's designs. This is due to tool performance limitations, which impose a bottleneck ...

Certify ASIC RTL Prototyping solution is the leading product for ASIC prototyping using multiple FPGAs. The Certify software is the industry's first register transfer level (RTL) prototyping solution ...

Santa Clara, CA -- June 01, 2016 -- Blue Pearl Software, Inc. a leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite 2016.2.

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched HES-DVM Proto Cloud Edition (CE).

Current ASIC design methodology traditionally is divided into two stages: front-end logical design and back-end physical implementation. The front-end typically includes the design capture, several ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...

Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting ...

As technology continues to evolve, the need for semiconductor chips also increases. The semiconductor industry lies underneath much of the technological progress, powering devices and systems that ...

Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought ...