EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 2)

Note: This is the second part of a two-part article covers the remaining steps to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions. Steps 4 ” ...
Security

AXIS T61 Audio and I/O Interface Series

Today, Axis Communications is announcing AXIS T61 Audio and I/O Interface Series, which enables audio and I/O connectivity to be added to Axis network cameras that don’t have this functionality ...
EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)

These design guidelines provide the best practices for DDR and DDR2 SDRAM custom memory interface implementation in Stratix III and Stratix IV FPGAs. Figure 1 shows the design flow that is required ...